The present invention relates to an analog-to-digital converter (ADC) with direct memory access (DMA) and in particular to an integrated circuit including an ADC with DMA.
As conversion times of ADCs reduce, increasing burdens are placed on processor time. In the preferred embodiment described below, for example, the conversion time of the ADC is 5 microseconds with the result that during continuous conversion (where the ADC immediately commences a new conversion after completing the previous conversion) the ADC is providing new conversion results at a rate of 200 KHz. For a typical microcontroller operating at 12 MHZ, dealing with conversion results at this rate may under prior art schemes, be an almost full time task. Conventionally, two possible methods of processing conversion results have been used.
Firstly, the conversion results may be processed by an interrupt routine. In this method, the ADC interrupts the microcontroller after each conversion. The microcontroller enters an interrupt service routine which reads the conversion results and stores them in memory. It will be appreciated that when the processing overheads associated with servicing an interrupt routine are taken into account, and bearing in mind that the microcontroller may need to read and write several words of data to store the full resolution of the conversion result, that very little (if any) processor time is available for the microcontroller to perform any other tasks.
Secondly, an alternative method is to cause the microcontroller to continuously poll a busy bit that busy bit being used by the ADC to indicate when a conversion is complete. It will be appreciated that the polling of the busy bit frequently enough not significantly to slow the continuous conversion rate of the ADC, places a considerable processing burden on the microcontroller. Thus, in common with the first method above, very little (if any) processing time is left for the microcontroller to perform other tasks.
Thus in the prior art techniques, the conversion rate of an ADC has been limited by the processing speed of an associated microcontroller.
In a first aspect, the present invention comprises an integrated circuit including a DMA controller, an ADC having a plurality of conversion channels, and address and data ports for connection to external memory means, the DMA controller being arranged to read a channel id from the memory means using the address and data ports which channel id is representative of one of the said conversion channels, to pass the read channel id to the ADC, to cause the ADC to perform an analog-to-digital-conversion on the conversion channel represented by the channel id, to receive the conversion result from the ADC and to write the conversion result back to the memory means using the address and data ports.
Thus by interacting with the DMA controller, a microcontroller may be relieved of the burden of storing ADC conversion results in the external memory means. Typically, the interaction will be performed via flags typically in a dedicated special function riser (SFR).
The DMA controller typically is implemented in the form of a state machine.
A particularly useful feature of the claimed invention is the ability to select channels of a multi-channel ADC without processor intervention. If the conversion results are written back to the same address in the memory means from which the channel id associated with that conversion result was read without corrupting the channel id stored at that address, the DMA controller may usefully be set to run through the same addresses to perform conversions on the same channels an unlimited number of times without requiring the microcontroller to write new channel ids to external memory before each continuous conversion occurs.
It will be appreciated that the term address is used to refer to a xe2x80x9cwordxe2x80x9d address. For example, in the preferred embodiment described below, the microcontroller has only an 8 bit data bus. The conversion result is, however, of 12 bits. Thus the conversion result spans 2 bytes and to read this word address the microcontroller must actually read 2 byte addresses. A consequence of this also in the preferred embodiment is that channel ids are written to alternate byte addresses before continuous conversion commences.
According to a first method aspect of the present invention, a method of performing a plurality of analog-to-digital conversions using an integrated circuit connected to memory means and having an ADC including a plurality of conversion channels and a DMA controller comprises pre-seeding the memory means with a predetermined sequence of channel ids each representative of a respective conversion channel, reading a first of the channel ids from the memory means, performing an analog-to-digital conversion on one of the plurality of conversion channels, the channel being selected according to a read channel id, writing the conversion result back to the memory means repeating the reading step with a subsequent channel id until the channel id is representative of an end instruction.
According to a further aspect, an integrated circuit includes a microcontroller having an output port, an address valid output line, a latch coupled to the output port, and a latch control line coupled to the latch control of the latch, the microcontroller being operable to present a first range of address bits at its output port to activate the latch control fine to cause the latch to latch the first range of bits, to present a second range of address bits it its output port and to activate the address valid line to indicate that the combination of the first and second ranges present on the latch outputs and the output port respectively, are valid.
In this way, with the inclusion of a minimal amount of additional hardware, a microcontroller having for example an 8 bit data or address bus may have the bit-width of that bus expanded. The output port may also output data first (which is latched) and then an address or vice versa.